Measuring system for comparing the relative magnitudes of first and second d.c. signals

ABSTRACT

A Measuring system for comparing the relative magnitudes of a first and a second D.C. input signal by symmetrically integrating the first input signal between time period intervals proportional to its magnitude relative to the magnitude of the second input signal so that pulses are generated at a frequency which is a multiple of the integrating cycle. The variable frequency pulses are either counted directly or are converted to a frequency variable train of voltage pulses, each of the pulse cycles of the train of pulses having the corresponding periodicity of the variable input frequency and each voltage pulse having a substantially constant pulse width; the train of pulses are used to modulate a voltage source output signal which, when subsequently averaged, provides an output signal that is proportional to the product of the modulated output signal of the voltage source and the input frequency.

United States Patent Krechmery et al.

[ Dec.26,1972

[54] MEASURING SYSTEM FOR Primary Examiner-Alfred E. Smith COMPARING THE RELATIVE Attorney-Joseph Maguire MAGNITUDES OF FIRST AND SECOND no. SIGNALS [571 ABSTRACT [72] Inventors: Roger L. Krechmery; Lee A. Measuring system for comparing relatiYe seabeck, both of Mentor Ohio mtudes of a first and a second D.C. input signal by symmetrically integrating the first input signal [73] Asslgnee: Bailey Meter Cnmpany between time period intervals proportional to its mag- [22] Filed: Sept. 11, 1970 nitude relative to the magnitude of the second input signal so that pulses are generated at a frequency [21] Appl' 7l508 which is a multiple of the integrating cycle. The variable frequency pulses are either counted directly or are Cl 235/ 61 converted to a frequency variable train of voltage pul- [5 1] Int. Cl. ..G01r 7/00 ses, each of the pulse cycles of the train of pulses hav- Field of Search 140 ing the corresponding periodicity of the variable input 235/194 frequency and each voltage pulse having a substantially constant pulse width; the train of pulses are used References Cited to modulate a voltage source output signal which, when subsequently averaged, provides an output UNITED STATES PATENTS signal that is proportional to the product of the modu- 3,500,200 3/ 1970 Woodhead ..324/ 142 lated output signal of the voltage source and the input frequency.

7 Claims, 8 Drawing Figures 56O I LINEARITY NETWORK 566 548 40 54s- T T l 266 240 520 I l l l VOLTAGE TO PULSE TO VOLTAGE T0 FREQUENCY VOLTAGE cuRRENT I I I l OONVERTER I CONVERTER OONVERTER DIFFERENTIAL SIGNAL j /L DIFFERENTIAL l CONVERTER l l T FEEESNER AMPL'F'ER E j z- Y AMPLIFIER m0 l8 isl R N l {SUPPLY WU 7 I i l F 227 Elli SENS RTE R0 I 546 E l l NDEMODULATOR :JEJVQCJ PRIMARY UNIT POWER SUPPLY DC l 547 54 1 i -|5v 0c 1 53 SECSIQIRARY +I3V 0c 1 T 5 POWFRSUPPLY MOVOC INVENTORS GER L. KRECHMERY LEE A. SEABECK PATENTEn DEC 26 m2 sumanrs 'IIIIHIIIIII PO Q PATENTED um 26 [972 SHEET 8 [IF 8 AMPLITUDE A SUPPLY VOLTIAGE AT I8 l8 0 PHASE gem: (DEGREES) 90 270 450 630 wt |s0 360 540 F 720 0 QUADRATURE VOLTAGE FLOW SIGNAL VOLTAGE AT I27 AT I27 DEMODULATOR VOLTAGE AT 2|2 Tut DEMODULATED QUADRATURE VOLTAGE AT 227 O l/ L/ wt DEMODULATED FLOW SIGNAL VOLTAGE AT 227 k 00 FLOW SIGNAL VOLTAGE 0 AT 238 REFERENCE COIL OUTEUT VOLTAGE PHASE ANGLE (DEGREES) PHASE SHIFTED DEMODULATED REFERENCE VOLTAGE AT 260 INVENTORS ROGER L. KRECHMERY BY LEE ASEABECK 00 REFERENCE VOLTAGE FIG. 6

PATENTED |972 3. 707.675

SHEET 8 UT 8 4A I I 2 2 3 3 3 7 7 *T T T T CONSTANT WIDTH +1 4 PULSES AT 458 2 A /T O l l l l I l to TI TI T2 t2 T3 t T4 T4 t t i t me OUTPUT PuLSES OF LOGIC AMPLIFIER 444 O LCONSTANT WIDTH OUTPUT PuLSES OF LOGIC AMPLIFIER 442 t T T T T T T- T- +T- 0 [VOLTAGE OUTPUT AT COLLECTOR 0F TRANSISTOR 470? 0 t VOLTAGE OUTPUT AT COLLECTOR OF TRANSISTOR 482\ F F- e T T T2 T2 T T3 VOLTAGE INPUT TO 2L +"g*"''+" *T VOLTAGE AVERAGING 7* NETWORK AT 5|5 APA O I l I I I l t I, I, t t t T t t t t t t I vOLTACE INPUT TO V0 E AvERACINC T T NETWORK AT VPA O T m FT DC CURRENT OUTPUT AT 548'548' t FOR APA OPERATION DC CURRENT 0U FOR V I VEN'TORS ATTORN MEASURING SYSTEM FOR COMPARING THE RELATIVE MAGNITUDES OF FIRST AND SECOND D.C. SIGNALS BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to measuring apparatus, which can be utilized in an electromagnetic flowmeter of the type in which an electrical signal is induced in a fluid flowing through a magnetic field, the electrical signal having a magnitude which, among other things, is directly proportional to the intensity of the magnetic field and the velocity at which the fluid is flowing through the field.

The invention is particularly applicable to measuring fluid flow through a conduit or liner and will be described with particular reference thereto although it will be appreciated that the invention has broader applications such as where the relative motion between the fluid and the magnetic field is the variable to be measured. The invention is thus suitable for measuring the rate at which a carrier of the measuring apparatus is moving through a fluid medium.

2. Description of the Prior Art Electromagnetic flowmeters have heretofore comprised exciter means for establishing a magnetic field substantially perpendicular to the direction of relative fluid motion, means for sensing an electrical signal induced by fluid flow through the magnetic field, and means for responding to the sensing means to provide an indication of fluid flow.

In such a flowmeter, the exciter means for establishing a magnetic field has taken the form of either a DC. exciter or an A.C. exciter. The DC exciter produces a magnetic field having a steady amplitude and direction, a DC. voltage being induced in the fluid having an instantaneous amplitude which is directly proportional to the velocity of fluid flow. In contrast, the A.C. exciter produces a magnetic field having a variable amplitude which alternates or periodically reverses its direction. An A.C. voltage of the same frequency as the exciter means is induced in the fluid having an instantaneous amplitude directly proportional to the velocity of fluid flow and phase shifted by an angle of +90 and -90, with respect to the phase of the A.C. exciter voltage, at opposite ends of a diameter of the fluid that is substantially normal to both the magnetic flux field and the direction of flow.

In both the DC. and A.C. exciter types of electromagnetic flowmeters, the means for sensing the electrical signal induced by fluid flow through the magnetic field has generally included a pair of electrodes electrically contacting the fluid, although magnetic field sensors not in contact with the fluid have also been used. In the electrode arrangement, the electrodes are usually placed at opposite ends of a diameter of a non-magnetic, electrically non-conductive conduit or liner through which the fluid to be measured flows. The electrode axis is oriented to be substantially normal to both the magnetic flux field and the direction of flow in order to sense the maximum electrical signal induced in the fluid.

It has been found in most applications that when using a DC. exciter means, the electrodes become polarized due to an accumulation of an electrical charge thereon, and this charge severely limits the accuracy of the flowmeter since it masks the DC. signal that is directly proportional to the velocity offluid flow. Frequent discharging of the electrodes is, at best, an intolerable solution to this problem.

The use of an A.C. exciter means prevents polarization of the electrodes by producing a magnetic field which periodically reverses its direction frequently enough to preclude the accumulation of charge. For practical operation, and to provide useful induced signals, even though they have a relatively small signal to noise ratio before amplification, the A.C. exciter means is generally preferred.

The means for responding to the sensing means to provide an indication of fluid flow have heretofore taken a variety of forms. These responding means have included primary means for balancing, isolatingly coupling and preamplifying the induced electrical signal from the sensing means along with secondary means, magnetically coupled to the primary means, to produce an output signal which provides a measurement of fluid flow.

One of the principal problems inherent in electromagnetic flow meters using A.C. exciter means is that the alternating flux induces error voltages of considerable magnitude in various parts of the system which mask the flow signal and cause the flowmeter to register other than zero for zero fluid flow. These error voltages may be grouped into two categories: namely, error voltages which are in phase with the induced flow signal, and error voltages which are in phase-quadrature out of phase) with respect to the induced flow signal. The in-phase error voltages are generally attributed to eddy currents being generated in the fluid and to artificial flow signals due to the apparent motion of the magnetic flux field with respect to a stationary fluid. The phase-quadrature error voltages are generally attributed to loop voltages magnetically coupled from the finite loop formed through the fluid by the electrodes and their connections along with capacitively coupled voltages from the exciter means. These error voltages are more or less interdependent and vary with the flow head structure and the conductivity and dielectric constant of the fluid to be measured.

Another important problem inherent in this type of electromagnetic flowmeter is caused by the amplitude and frequency fluctuations from conventional sources of power which generally are used to supply power to the exciter means. When the amplitude and frequency of the source of power are not perfectly controlled, the magnetic flux field produced by the exciter means will fluctuate accordingly, and the flow signal induced in the fluid will not provide a useful indication of the velocity of fluid flow. It is, therefore, desirable to provide a reference means which will compensate for both the amplitude and frequency fluctuations of the exciter means in order to provide an accurate measurement of fluid flow.

The ultimate problem in the design and operation of an electromagnetic flowmeter is in the selection and integration of component elements into a flowmeter system which overcome all of the above-referred problems, and others, and which inherently does not present insoluble problems. Heretofore, devices have been known which will convert an A.C. signal to a proportional D.C. signal coupled to other devices which lObOlZ 0l86 can generate pulses having a frequency more or less proportional to that signal, but such systems have been thought to'be generally rather non-linear, inaccurate, and subject to drifts, and, for these reasons, have not been successfully used in flowmeter systems.

The present invention contemplates a new and improved apparatus which overcomes all of the abovereferred problems, and others, and provides a measuring system which is stable, linear and accurate.

SUMMARY OF THE INVENTION In accordance with the present invention, a measuring system for comparing the relative magnitudes of a first and a second D.C. input signal is provided, comprising: means for symmetrically integrating the first D.C. signal between time period intervals proportional to its magnitude relative to the magnitude of the second DC. signal; switching means for periodically reinitiating the symmetrical integrating cycle; and, pulse generating means responsive to the half-period cycles of the symmetrical integrating means so that output pulses are generated at a frequency which is a multiple of the integrating cycle.

Further, in accordance with the invention, a frequency to voltage converter is provided, including: means for producing a frequency variable train of pulses, each of the pulse cycles of the train of pulses having the corresponding periodicity of the variable input frequency and each pulse having a substantially constant pulse width; means for voltage converting the pulse cycles of the train of pulses to form a substantially square wave signal varying plus and minus of a reference level, the deviations of one polarity having a substantially constant width synchronized with the constant width pulses and the deviations of the other polarity being synchronized with the remainder of each pulse cycle; a voltage source having an output signal; series-shunt chopper means coupled to the square wave signal for modulating the voltage source output signal during the deviations of one polarity; and means for averaging the modulated output signal of the voltage source to provide an averaged output voltage which is proportional to the product of the modulated output signal of the voltage source and the input frequency.

In accordance with a more limited aspect of the invention, a phase sensitive demodulator is provided, including: means for synchronizing the phase of an A.C. signal with the phase of the induced'flow signal and series-shunt chopper means, coupled to the A.C. signal from the synchronizing means, for demodulating halfcycles of the induced flow signal and for rejecting error signals which are in phase-quadrature with the flow signal.

The principal object of the present invention is to provide a measuring system which produces a stable, linear and accurate response indication which is particularly suitable for fluid flow measurement.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the invention as used in an electromagnetic flowmeter.

FIG. 2 is a schematic diagram of the primary circuits in the flowmeter.

FIGS. 35 inclusive form a conjoint schematic diagram of the secondary circuits in the flowmeter.

FIG. 6 is a view of wave forms representing various operating characteristics of the circuits in FIGS. 2 and FIG. 7 is a view of several wave forms representative of various points in the voltage to frequency converter circuits of FIG. 4.

FIG. 8 is a view of several wave forms representative of various points in the circuits of FIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings wherein the showings are for' the purposes of illustrating the preferred embodiments of the invention only and not for the purposes of limiting same, FIG. 1 is a block diagram illustration of the invention as used in an electromagnetic flowmeter which provides an indication of fluid flow.

, I The present flowmeter includes a primary unit A and a secondary unit B. The primary unit A includes a flow head assembly 10 with a zero flow balance circuit 20, a differential source follower 50 and a differential amplifier proximately located thereto. The secondary unit B is coupled to the primary unit A by a transformer 106, and the secondary unit B includes a signal converter amplifier 120, a phase sensitive demodulator 130, a reference voltage circuit 40, a voltage to frequency converter 240, a pulse to voltage converter 430, and a voltage to current converter 520. The present flowmeter is adapted to measure mass flow by the inclusion of a density gage 11 in the primary unit A coupled to a linearity network 560 in the secondary unit B.

A conventional A.C. source of power is connected across terminals 18, 18' in order to provide the operating power for the flowmeter system. A suitable and readily available supply voltage for the flowmeter system is l 18 $10 volts A.C. with a frequency of 50 fl or 60 :5 cycles per second (cps). It should be recognized that it is within the ability of a skilled worker in the art to make the necessary modifications in the system in order for it to operate on various other supply voltages and supply frequencies for particular applications wherein this is deemed necessary. The supply voltage is coupled through a transformer 546 to a primary unit power supply 548 which may take the form of a conventional full wave rectifier and filter circuit arranged to provide two DC. voltage outputs of equal magnitude and opposite polarity. A regulated +15 volts and l5 volts is provided in this way by the primary unit power supply 548 in order to supply the operating voltages for primary unit A. The supply voltage is also coupled through a transformer 550 into a secondary unit power supply 552 in order to provide three DC. voltage outputs, +40 volts, +13 volts and l3 volts. The three voltages from the secondary unit power supply 552 provide the operating voltages for the secondary unit B of the flowmeter system. The provision of the primary and secondary unit power supplies insures that the primary unit is isolated from the secondary unit. Just as with the magnitude of the supply voltage, the particular values of voltages specified for the power supplies 548, 552 is not critical to the principle on which the flowmeter system operates, but is specified merely to provide a complete and adequate disclosure.

The input supply voltage is also coupled through transformer 158 into the phase sensitive demodulator 130, and the secondary winding of each of the transformers 106, 158 and 550 are center-tapped at 113, 163 and 551, respectively, and connected in common by a conductor 117 which provides the ground reference for the secondary unit B. The ground reference for the primary unit A is taken from a center tap 547 of transformer 546 and this point is also connected to the case of transformer 106 by conductor 115 in order to shield the primary unit A from the secondary unit B.

The voltage to current converter 520 in the secondary unit B is particularly suited to provide a DC. output current at terminals 548 548 in the range of either 4-20 milliamperes (ma) or l0-50 ma in order to be compatible with the use of conventional DC. current responding indicators of a precise nature.

THE PRIMARY UNIT A schematic diagram of the primary unit A of FIG. 1 is illustrated in FIG. 2. The flow head assembly 10, the zero flow balance circuit 20, the differential source follower 50 and the differential amplifier 90 are correspondingly numbered. The flow head assembly includes a non-magnetic, electrically nonconductive conduit or liner 12 through which the fluid to be measured flows. Exciter means for establishing a magnetic field substantially perpendicular to the direction of relative fluid motion takes the form of a pair of coils 16, 16 which are shown connected in parallel across the supply voltage terminals 18, 18. The use of primed numbers should be understood to designate symmetry in parameters, structure and function with respect to the elements designated by the corresponding unprimed numbers.

A means for sensing an electrical signal induced by fluid flow through the magnetic flux field generated by the A.C. voltage applied to the coils 16, 16' takes the form of electrodes 14, 14' at opposite ends of a diameter of the conduit 12 and oriented perpendicularly with respect to the magnetic flux field generated by coils 16, 16'. The electrodes 14, 14 are placed in electrical contact with the fluid flowing through liner or conduit 12 in order to sense the electrical signal induced in the moving fluid flowing through the magnetic flux field in the conduit 12 according to Faradays law of electromagnetic induction. The design of coils 16, 16' may be such as to provide either a uniform magnetic field within the flow conduit 12 in the region of the electrode axis 14, 14' or a non-uniform field distribution. The choice of coil design, providing uniform magnetic fields, depends largely on whether or not the fluids to be measured will have an axis symmetrical velocity profile in the effective magnetic field within the conduit l2. Axis symmetrical velocity profile refers to a constant value of fluid velocity around the periphery of any circle with an arbitrary radius measured from the flow axis in a plane perpendicular to the flow axis and within the domain of the effective magnetic field. A particularly well suited coil design for establishing a uniform magnetic field within the conduit 12 is disclosed and claimed in a copending US. application, Ser. No. 77,905, filed Oct. 5, 1970. A coil design of this type may be used for producing a uniform magnetic field as defined in this copending US. APPLICATION.

The electrode 14 is connected to a pair of conductors 42 which are formed into a loop perpendicular to and within the domain of the magnetic field established by coils 16, 16'. The conductors 42 are twisted together at 44 and are connected across a potentiometer 46 having a movable contact arm 47. A similar pair of conductors 42' are connected to electrode 14' and are twisted at 44' and connected across potentiometer 46 having a movable contact arm 47'. The movable contact arms 47, 47' are connected through coupling capacitors 52, 52 respectively into the respective inputs of the differential source follower 50. A metallic shield 45 driven at point 60 by the differential source follower 50 extends from the connection at the differential source follower 50 to the loop formed by conductors 42 in the vicinity of the electrode 14. This arrangement provides an effective shield to prevent picking up stray signals which would reduce the effective capacitance of the cable and substantially eliminates the introduction of stray signals into the differential source follower 50. A similar shield arrangement 45 is provided for the coupling between electrode 14' and coupling capacitor 52.

According to Faradays law, the voltage induced in the fluid by its motion with respect to the magnetic field has an instantaneous value which is proportional to the mean velocity of fluid flow but has a phase difference of with respect to the instantaneous magnitude of the A.C. magnetic flux field through which it flows. The effect of the conductor loops 42, 42 exposed to the magnetic field is thus to purposely pick up a voltage caused by the changing magnetic field and superimpose this voltage with the voltage sensed by the electrodes in contact with the fluid. The provision of potentiometers 46, 46', connected to the loops 42,42, forms an electrical bridge which can be balanced by adjustment of movable contact arms 47, 47' in order to eliminate the quadrature voltage that would otherwise be conducted to the inputs of the differential source follower 50. When the potentiometer 46 is properly adjusted, the signal at its movable contact arm 47 will be the signal sensed by electrode 14, and, similarly, when potentiometer 46 is properly adjusted, the signal on its movable contact arm 47' will be the signal sensed by the electrode 14'. A metal grounding shield 48 is provided so as to encircle the driven shield 45, 45' in order to further eliminate capacitively coupled signals between the inputs to the differential source follower 50. The shield 48 may either be grounded to the primary unit A ground reference at point 49 or may be connected to a third electrode in the conduit 12 placed on a line bisecting the axis formed by the electrodes 14, 14. The third electrode, like the electrodes 14, 14', is placed in electrical contact with the fluid flowing through conduit 12, but it does not sense an electrical signal induced in the fluid because it is oriented parallel to the direction of the magnetic field generated by coils 16, 16. The third electrode, therefore, would only serve to provide a fluid reference ground for the metallic grounding shield 48.

The zero flow balance circuit 20 includes a pair of coils 22, 22', each having one of their terminals connected in common at point 23. The coils 22, 22 are disposed symmetrically with respect to the common axis joining the exciter coils 16, 16' and interposed between the flow conduit 12 and either of these exciter coils. The balance coil 22 is connected to a fixed contact 26 of a single pole, double throw switch 24, and the remaining terminal of balance coil 22' is connected to the other fixed contact 25 of switch 24. The switch 24 has a movable switch arm 28 which is connected to a potentiometer 30, and the other terminal of potentiometer 30 is connected by a conductor 34 to the movable contact arm 32 of potentiometer 30. The movable contact 32 is connected to the common terminal connection 23 between coils 22, 22. 4

The zero flow balance circuit 20 is adjusted by varying the position of the movable contact arm 32 of potentiometer 30 in order to eliminate in-phase error voltages generally due to eddy currents generated in the fluid and artificial flow signals due to the apparent motion of the magnetic flux field with respect to a stationary fluid. When the movable switch arm 28 contacts fixed contact 25, a variable resistance in series with coil 22 is provided. It is then possible to introduce a variable resistive loss in this circuit by moving contact arm 32 until the inphase error voltages are eliminated.

[fit is not possible to eliminate these error voltages with the movable switch arm 28 in this position, the movable switch arm 28 is shifted so that it contacts fixed contact 26 so as to form a series circuit with coil 22. The movable contact arm 32 is again adjusted until the in-phase error voltages are eliminated from the flow signal. The operation of balancing coils 22, 22 in this way makes it possible to provide a solid zero flow signal to the input of differential source follower 50. This makes it possible for the flowmeter to operate substantially independent of the conductivity and dielectric constant of the fluid to be measured. A simple adjustment of movable contact arm 32 compensates for the characteristics of different fluids flowing through the conduit 12. It should be recognized that the same result may be achieved by operating coils 22, 22' simultaneously by connecting potentiometer directly across the coils 22, 22 and changing the position of the movable contact arm 32 so as to introduce an unequal resistance into both legs of the circuit thus formed.

The action of the zero flow balancing circuit 20, as described above, also tends to eliminate losses which are non-homogenous and are caused by lack of symmetry in the magnetic structure of the flow head assembly l0 and the fluid to be measured. This lack of symmetry can cause a rotating flux vector to'exist in the area of electrodes 14, 14', and this produces a fictitious flow signal at zero fluid flow. The magnetic coupling action between the balancing coils 22, 22' and the exciter coils 16, 16' symmetrizes the losses and causes the rotating flux vector to stop, thus providing a zero output at zero flow.

The flow head assembly 10 also includes a pair of reference coils 36, 36' connected in parallel and providing a voltage signal at the output terminals 38, 38'. The voltage signal at terminals 38, 38' is conducted to the reference voltage circuit 40 located in the secondary unit B of FIGS. 1 and 3, and a description of its function therein will be considered with reference to FIG. 3. The windings of coil 36 are contiguous with the windings of exciter coils 16 except for an insulating medium electrically isolating the coils. The voltage applied to coil 16 is thus coupled by transformer action to coil 36 in a 1:] ratio, and a similar coupling of the voltage applied to coil 16' is induced in coil 36' so that the voltage at the reference coil output terminals 38, 38' is of the same magnitude as the exciter voltage and also has the same frequency. The I usefulness of this reference signal will be discussed hereinafter.

The substantially error-free signal voltages from the flow head assembly 10 are coupled into the differential source follower 50 through coupling capacitors 52, 52'. Since the remainder of the circuits in the primary unit A are substantially symmetrical with respect to their operation on each of the flow signals, the description of the remainder of primary unit A in FIG. 2, with minor exceptions, will be with reference to the elements designated by unprimed numbers. The coupling capacitor 52 is connected to a gate terminal (G) of a field effect transistor (FET) 54 also having a drain (D) terminal and a source (S) terminal designated accordingly. The FET 54 is a member of a class of transistor devices which may be switched from a low resistance state to a high resistance state by the application of a potential difference between two of its terminals. The FET 54 is of the type known as N-channel in that the resistance from the drain to source terminals switches from a low to high resistance state when the potential difference between the gate to source terminals is changed from zero to a negative value, thus diminishing the drain current of the device. The N- channel FET 54 is generally biased so that the drain terminal is positive in potential with respect to the source terminal.

A resistor 56 is connected between the junction cominon to coupling capacitor 52 and the gate terminal of the FET 54, and a resistor 64 is connected to its remaining terminal in order to provide a series circuit leakage path therethrough and through conductor 66 to reference point 68 for the primary unit A. The junction between resistors 56, 64 is connected through conductor 58 to the signal shield 45 at point for the driving point connection. This junction between resistors 56, 64 is also connected to a capacitor 60 which has its remaining terminal connected to the source terminal of PET 54. The drain terminals of FETs 54, 54 are connected in common by conductor 76, and these drain terminals are maintained at a positive source of potential by the connection through conductor 78 to a regulated D.C. voltage as provided by primary unit power supply 548.

The differential source follower 50 also includes a pair of D.C. current generators generally designated 70. A current generator here includes an NPN transistor 72 having base (b), emitter (e) and collector (0) terminals correspondingly designated. The base of transistor 72 is connected to the base of a similar transistor 72' by conductor 73. The emitter of transistor 72 is connected to a bias resistor 84 which is connected through a conductor 86 to a source of D.C. potential negative in polarity with respect to the source of potential connected to the drain terminals of FETs 54, 54. The magnitude of this negative source potential is regulated so as to have the same magnitude as the above-mentioned positive source of potential in the primary unit power supply 548. The emitter of transistor 72 is connected through a bias resistor 84 which has the same value of resistance as resistor 84 and is also connected to conductor 86. A Zener diode 80 has its anode terminal connected to the base terminals of transistors 72, 72' through conductor 73 and its cathode terminal connected to the ground reference point 68 for the primary unit A. The collector terminal of transistor 72 is connected to the source terminal of' FET 54 through conductor 74, and this collector terminal is also connected through a coupling capacitor 88 to the input of the differential amplifier 90.

The DC. current generators 70 as above described in such as to provide current sources which act as high, dynamic resistors rather than constant value resistors. The differential source follower 50 thus operates as a high input impedance device in order to isolate the flow head assembly from the differential amplifier 90, as well as for driving the signal shields 45, 45' and providing a unity gain for the flow signal.

The coupling capacitors 88, 88' function to eliminate any D.C. component of the isolated flow signal from being coupled to differential amplifier 9 in the same way that coupling capacitors 52, 52' eliminate any D.C. component of the balanced flow signal from being coupled to the input of the differential source follower. The differential amplifier 90 includes a pair of operational amplifiers 92, 92 connected for push-pull operation. The isolated flow signal coupled through capacitor 88 is connected to the positive input terminal of operational amplifier 92, and a biasing resistor 94 is connected from this positive input terminal to the ground reference 68 for the primary unit A. The output terminal of operational amplifier 92 is connected through a high frequency noise filter including resistor 96 and capacitor 98 connected in parallel and in feedback through conductor 99 to the negative input terminal of operational amplifier 92. The positive terminal of a polarized capacitor 104 is also connected to the output terminal of operational amplifier 92, and its negative terminal is connected through the primary winding 108 of an output transformer 106 to the nega tive terminal of a series opposing polarized capacitor 104 which in turn has its positive terminal connected to the output terminal of operational amplifier 92'. The operational amplifier 92 also has a high frequency noise filter including a resistor 96 and a capacitor 98 connected in parallel and in feedback through conductor 99' to the negative input terminal of operational amplifier 92'.

The differential amplifier 90 has a common gain adjusting network for both operational amplifiers 92, 92 connected between the negative input terminals of both of these amplifiers. The common gain adjusting network includes resistors 100 and 101 connected in series between conductors 99, 99 and a potentiometer 102. The potentiometer 102 has a movable contact arm 103 and one of its remaining terminals connected in common to conductor 99 and the other terminal connected to the junction between resistors 100 and 101. The structure of the differential amplifier 90 as described is such as to provide the same value of input impedance to the flow signals coupled through capacitors 88, 88, and, therefore, equal loading on each leg of the differential source follower 50. This differential amplifier circuit also provides enhanced common mode rejection characteristics so as to eliminate any false signals from being produced at the output terminals of operational amplifiers 92, 92'.

The output transformer 106 of the primary unit A also includes a secondary winding 112 and a case shield 110 which is connected at point 114 and by conductor 115 to the primary reference ground 68. The secondary winding 112 is center tapped at point 113 in order to provide the secondary reference ground 117 for the secondary unit B in FIG. 1 and is also shown in the conjoint schematic diagram of FIGS. 3-5 inclusive. The transformer 106 is chosen to have a voltage gain from the primary winding 108 to the secondary winding 112 of about 1:1.5 so that a maximum flow rate signal of 300 millivolts on the primary winding 108, gain adjusted by potentiometer 102, will provide a 250 millivolt peak to peak voltage signal between center tap 113 on the secondary winding 112 and terminals 116 and 116'. The use of the transformer 106 also provides isolation for the secondary unit B which may be located remotely from the primary unit A.

THE SECONDARY UNIT Referring now to FIG. 3, the signal converter amplifier 120, the phase sensitive demodulator 130 and the reference voltage circuit 40, included in the secondary unit B of FIG. 1, are schematically illustrated. The signal converter amplifier 120 includes a first stage of differential amplification 122 coupled to a second stage of differential amplification 126 through a span adjustment potentiometer 124; an averaging amplifier circuit 128 is coupled from the second stage of differential amplification 126 through the phase sensitive demodulator 130 in order to provide a DC. output signal at terminal 238 which is proportional to the flow signal coupled from the primary unit A.

The first stage of differential amplification 122 includes an operational amplifier 136 having its negative input terminal connected through an input resistor 132 from the secondary terminal 116 of transformer 106. The transformer secondary terminal 116 is connected to an input resistor 134 which is in turn connected to the positive input terminal of operational amplifier 136. This positive input terminal is also connected through a bias resistor 138 to the conductor 117 from the center tap 113 of transformer 106 and serves as the secondary reference ground for the entire secondary unit B. The output terminal of operational amplifier 136 is connected through a feedback resistor 140 to its negative input terminal. A polarized capacitor 142 has its positive terminal connected to the output terminal of operational amplifier 136, and its negative terminal is connected to the negative terminal of a second polarized capacitor 144. The capacitor 144 has its positive terminal connected in series with the span adjustment potentiometer 124 which is referenced to conductor 117. The movable contact arm 125 of the span adjustment potentiometer 124 is connected through a conductor 146 to the positive input terminal of an operational amplifier 148 which is included in the second stage of differential amplification 126. The output terminal of operational amplifier 148 is connected through a voltage dividing network including a calibrated adjustment potentiometer 150 in series with a resistor 152 which is also in series with a resistor 154. The junction between resistor 152 and 154 is connected through a conductor 156 to the negative input terminal of operational amplifier 148. The movable contact arm 151 of the calibrated adjustment potensecondary winding 162 having a center tap at 163. The

phase shifting network 164 includes a capacitor 174 connected between one terminal of the secondary winding 162 and the negative input terminal of operational amplifier 166. The remaining terminal of secondary winding 162 is connected through potentiometer 178, having a movable contact arm 179 connected to its remaining terminal, the junction of these terminals also being connected to the negative input terminal of operational amplifier 166 through conductor 180. A center tap of the secondary winding 162 at point 163 is connected to the positive input terminal of the operational amplifier 166, and their junction is connected through conductor 183 to the secondary reference ground conductor 117. The effect of adjusting contact arm 179 is to shift the phase of'the A.C. voltage signal introduced in the secondary winding 162 and applied to the input terminals of the operational amplifier 166. This provides that the output voltage of the operational amplifier 166 is exactly in phase with respect to the fiow signal voltage in its A.C. form at the output terminal of operational amplifier 148.

The output terminal of operational amplifier 166 is connected through a resistor 184, througha resistor 188 and a capacitor 190, connected in parallel, to the base of an NPN transistor 192. The junction between resistor 184 and the parallel combination of resistor 188 and capacitor190 is connected to the cathode of a Zener diode 186 having its anode connected to the reference ground conductor 117. The emitter of transistor 192 is connected to conductor 117, and its collector is connected through a resistor 194, through a conductor 196 to a positive DC voltage supplied by the secondary unit power supply 552 in FIG. 1, The circuit described above is included in the clamper amplifier 168 which is used to clamp the output voltage from operational amplifier 166 to a useful level as well as providing an increased switching speed between low and high voltage levels. This latter effect is enhanced by the use of the parallel combination of resistor 188 with capacitor 190.

The output signal from the clamper amplifier 168 is connected from the collector of transistor 192 through a resistor 198, in parallel with a capacitor 200, to the base of a PNP transistor 202. The emitter of transistor 202 is connected to the cathode of a diode 204 which has its anode connected to the positive DC. voltage supplied to the collector of transistor 192. The emitter of transistor 202 is also connected through a resistor 206 to the reference ground conductor 117. The collector of transistor 202 is connected through a resistor 208 to a negative voltage source included in the secondary unit power supply 552. The circuit thus described is included in the inverter amplifier 170 and provides a square wave output signal at the collector terminal of transistor 202. This output signal has a frequency equal to the frequency of the amplified flow signal at the outputterminal of operational amplifier 148 and is directly in phase therewith.

The collector of transistor 202 is connected by a conductor 212 to the input of the series-shunt chopper circuit 172. The series-shunt chopper circuit 172 includes a P-channel FET 214 having its gate terminal connected to the cathode of a diode 216 which has its anode connected to conductor 212. A capacitor 218 is connected in parallel across diode 216. The drain terminal of PET 214 is connected to the output of operational amplifier 148 by conductor 127, and its source terminal is connected to conductor 227 which forms one of the inputs to the averaging amplifier circuit 128. An N-channel FET 220 is connected so as to be in shunt between conductor 227 and the reference ground conductor 117. The source terminal of FET 220 is connected through conductor 226 to the source terminal of PET 214, and the drain terminal of PET 220 is connected directly to conductor 117. The gate terminal of PET 220 is connected to the anode of a diode 222 which has its cathode connected to a conductor 212, and a capacitor 224 is connected in parallel with diode 222. The effect of the series-shunt chopper circuit in conjunction with the symmetrical square wave voltage signal at the collector of transistor 202 provides a relatively low series resistance between the drain-source terminals FET 214. This arrangement passes negative half cycles of the flow signal on conductor 127 to conductor 227 and into the negative input of the averaging amplifier circuit 128 while simultaneously presenting a relatively large shunt resistance between the drain-source terminals of PET 220 to effectively act as an open circuit during negative half cycles of the flow signal. During positive half cycles of the flow signal, the drain-source resistance of PET 214 is relatively high so as to present substantially an open circuit between conductors 127 and 227. At the same time, the drain-source resistance of PET 220 is relatively low in order to provide a shunt path to the reference ground conductor 117 for substantially eliminating any of the positive half cycles of the flow signal from being conducted to the input of the averaging amplifier circuit 128. The series-shunt chopper circuit operating in this fashion thus provides negative half cycles of the flow signal to the input of the averaging amplifier circuit 128, and its operation may be likened to that of a half-wave rectifier with the following important distinction. The overall operation of the phase sensitive demodulator 130 rejects any quadrature signal 'component present at the output terminal of operational amplifier 148 which has not been rejected by the preceding circuitry or which has been introduced during the previous functional operations on the flow signal.

The averaging amplifier circuit 128 includes an operational amplifier 230 having its negative input terminal connected to an input resistor 228 which is also connected to conductor 227. The positive input terminal of operational amplifier 230 is connected to a bias resistor 232 connected to. the reference ground conductor 117. A resistor 234 is connected in feedback between the output terminal of operational amplifier 230 and its negative input terminal, and a capacitor 236 is connected in parallel with resistor 234 inorder to provide the averaging operation to the negative half cycles of the flow signal from conductor 227. The output of operational amplifier 230 at terminal 238 provides one of the inputs to the voltage to frequency converter 240 in FIGS. 1 and 4.

The various operating characteristics of the flowmeter circuits described above, including the signal converting amplifier 120 and the phase sensitive demodulator 130 may be more thoroughly understood by reference to FIG. 6 (A)(F). FIG. 6 is intended to show the relative phase angle and polarity with respect to various wave forms in the flowmeter system but is not intended to show the relative amplitude of these wave forms. FIG. 6(A) shows two cycles of the A.C. sinusoidally alternating supply voltage at the input terminals 18-18 of FIG. 1. This voltage wave form may also be considered to represent the voltage on the primary winding 160 of transformer 158 for the phase sensitive demodulator 130 as well as the voltage for the exciter coils 16-16' in the flow head assembly 10. The abscissa (w t) represents the phase angle in degrees and is graduated in increments of 90.

Referring now to FIG. 6(B), the flow signal voltage wave form on conductor 127 is shown to be shifted 90 electrical degrees lagging with respect to the instantaneous phase angle of the wave form in FIG. 6(A). A phase quadrature voltage component on the conductor 127 is shown to have a phase angle identical to the phase angle of the wave form in FIG. 6(A). This quadrature voltage on conductor 127 may be considered to have a relatively small instantaneous amplitude because of the effect of the quadrature-balancing elements in the flow head assembly when they are properly adjusted. A point by point summation of the flow signal voltage and the quadrature signal voltage in FIG. 6(B) would provide a representation of the actual wave form on conductor 127, but for purposes of illustrating the effect of the phase sensitive demodulator 130, the flow signal voltage and the quadrature voltage may be considered independently as illustrated.

FIG. 6(C) shows the demodulator voltage on conductor 212 which drives the series-shunt chopper circuit 172. The action of the series-shunt circuit 172, by changing the resistance of FETs 214 and 220, demodulates the flow signal voltage at 127, and this results in the negative half cycles of flow signal voltage on conductor 227 as shown in FIG. 6(E). The component of quadrature voltage on conductor 127, between the phase interim of 90-270 and between 450630, as well as the positive flow signal voltage on conductor 127 between these phase interims is completely eliminated. The components of demodulated quadrature voltage on conductor 227, which remain after the action of the phase sensitive demodulator 130, have a negative component below the abscissa which is equal to a positive component above the abscissa as shown in FIG. 6(D). The average value of the demodulated quadrature voltage on conductor 227 is, therefore, equal to zero; whereas, the demodulated flow signal voltage on conductor 227 is shown to have a negative value. After the wave form shown in FIG. 6( E) is processed through the averaging amplifier circuit 128, the wave form shown in FIG. 6(F) is the result, and this wave form is representative of the DC. flow signal voltage at terminal 238. The voltage wave form shown in FIG. 6(F) is variable over positive values and is proportional to the A.C. flow signal voltage.

An alternative arrangement for the phase sensitive demodulator 130 provides a direct connection from the output terminal of operational amplifier 166 to the conductor 212, driving the series-shunt chopper circuit 172, and thus eliminating resistor 184, clamper amplifier 168 and inverter amplifier 170. The amplifiers 168, 170 serve mainly to speed up the switching from negative to positive values, and vice versa, of the voltage on conductor 212. These amplifiers may be eliminated with the proviso that the operational amplifier 166 is of sufficiently high gain and is rapid enough in operation to provide a square wave voltage at its output terminal which will properly drive the series-shunt chopper circuit 172. The circuit thus described, including signal converter amplifier and phase sensitive demodulator in its modified form, will thus operate in substantially the same fashion as described above in order to provide a DC. signal voltage at terminal 238 which is substantially free of any quadrature component.

The reference voltage circuit 40, also illustrated in FIG. 3, includes a low pass filter 242, a precision half wave rectifier circuit 246 and an averaging amplifier circuit 248. The low pass filter 242 includes a resistor 249 connected in series to terminal 38 and a capacitor 250 connected in shunt with respect to the other terminal of resistor 249 and the reference coil terminal 38'. The output voltage across capacitor 250 may be written as a function of the input voltage at terminals 38,38 according to equation l 0250 sa-as' 'j 'fR249 25o) (I) Where:

V0250 the voltage across capacitor 250 13 the reference coil output voltage at terminals 38-38 j= V l the complex operator f the reference coil supply frequency in cyclesper second R the value of resistor 249 in ohms, and C the capacitance of capacitor 250 in farads If the second term in the denominator of equation (I is large with respect to l, the first term in the denominator, this equation can be written as equation 0250 ESE-38' (l f 249 25u) (2) Equation (2) shows that for constant values of resistance and capacitance, the voltage across capacitor 250 varies directly proportional to the reference coil output voltage and inversely proportional with respect to the frequency of the reference coil output voltage. This effect is important since the ultimate purpose of the reference voltage in the flowmeter system is to provide a comparison voltage which will compensate for supply voltage changes in peak amplitude and frequency. As will be subsequently described, the provision of the low pass filter 242 at the input to the reference voltage circuit 40 fully compensates for these changes in the supply voltage in order to provide an accurate measurement of fluid flow.

The common junction between resistor 249 and capacitor 250 is connected to a resistor 251 which is in turn connected to the negative input terminal of an operational amplifier 252 included within the precision half wave rectifier circuit 246. The positive input terminal of operational amplifier 252 is connected through abias resistor 253 through a conductor 254 to the ground reference conductor 117. Conductor 254 is also connected to the junction between terminal 38 and capacitor 250. The rectifier circuit 246 also includes two feedback paths between the output terminal of operational amplifier 252 and its negative input terminal. The first feedback circuit includes a resistor 258 connected to the anode of a diode 257 having its cathode connected to the output terminal of operational amplifier 252. This cathode is also connected to the anode of a diode 255 having its cathode connected to a resistor 256 which completes the second feedback circuit. The junction common to the cathode of diode 255 and resistor 256 is connected through a compensator potentiometer 259 having a movable contact arm 260 connected to one of its terminals and a resistor 261 which forms an input to the negative input terminal of an operational amplifier 262 included within the averaging amplifier circuit 248. The positive input terminal of operational amplifier 262 is connected through a bias resistor 263 to the reference ground conductor 1 17. A feedback resistor 265 is connected in parallel with a capacitor 264 between the output terminal of the operational amplifier 262 and its negative input terminal, and output terminal 266 forms a second input to the voltage to frequency converter 240 shown in H68. 1 and 4. The compensator potentiometer 259 is adjustable to provide adjustment of the D.C. reference voltage output at terminal 266. Without this adjustment, capacitor 250 would be required to have a very close tolerance. Since temperature stability is desired in the reference voltage circuit 40, capacitor 250 is chosen to be temperature stable.

Temperature stability is accomplished for the remainder of the reference voltage circuit 40 by energizing operational amplifier 252 within the reference voltage circuit 40 from the same source of supply voltage as used for operational amplifier 148 in the signal converter amplifier 120. Operational amplifiers 262 and 230 are similarly energized. Temperature stability and the elimination of drift problems in the D.C. output voltages at terminals 266 and 238 are further enhanced by substantially matching the averaging amplifier circuits 248 and 128. This matching includes providing capacitors 264 and 236 which are equal in value and doing the same for resistors 265 and 234.

Referring again to FIG. 6, and, in particular the wave forms shown in (G)-(l), FIG. 6(G) shows two cycles of the sinusoidal AC. voltage at terminals 38, 38. It should be noted that the reference coil output voltage is in phase with the supply voltage shown in wave form (A) of this figure. FIG. 6(H) shows the wave form for the demodulated reference voltage at the movable contact arm 260, and it is shown shifted an amount equal to approximately 90 electrical degrees phase lagging with respect to the instantaneous phase of the wave form shown in FIG. 6(G). This phase shift is due to the relative magnitude of the parameters for resistor 249 and capacitor 250 and is further accounted for by the inclusion of the complex operator j in equations (1) and (2). The reference voltage circuit 40, unlike the phase sensitive demodulator 130, is not phase sensitive. The reference voltage circuit 40 is, however, sensitive to the magnitude of the magnetic flux field generated within the flow conduit 12. It is also sensitive to the frequency of this magnetic flux field since both are inter-dependent on the supply voltage and thus have a direct effect on the flow signal induced in the field to be measured. The wave form shown in FIG. 6(l) represents the negative polarity D.C. reference voltage at terminal 266 after averaging and inversion by passing the wave form of FIG. 6(l-l) through the averaging amplifier circuit 248. The level of the D.C. reference voltage varies over negative values corresponding to the amplitude and frequency changes of the supply voltage. The level of this reference voltage may be adjusted by adjusting the contact arm 260 of the compensator potentiometer 259 in order to modify the amplitude of the input signal to operational amplifier 262.

The D.C. reference voltage at terminal 266 is adjusted to be substantially equal to the D.C. flow signal voltage at terminal 238 when this latter voltage is at a positive value corresponding to the maximum rate of flow. The span adjustment potentiometer 124 in the signal converter amplifier provides adjustment for full scale deflection of the flow signal voltage to adjust the sensitivity of the flowmeter. The calibrated adjustment potentiometer 150, also located within the signal converter amplifier 120, provides added flexibility for calibration purposes.

VOLTAGE TO FREQUENCY CONVERTER Referring now to P16. 4, the voltage to frequency converter 240 is connected at terminal 238 to the D.C. flow signal voltage converter amplifier 120. It is also connected at terminal 266 to the D.C. reference signal voltage from the reference voltage circuit 40. The voltage to frequency converter 240 includes a dual integrator ratio circuit 268, a voltage divider and regulator network 310 and a frequency doubling circuit 376. The voltage to frequency converter 240 provides a variable duty cycle pulse output at an output terminal 428 which varies proportional to the ratio of the DC. flow signal voltage with respect to the D.C. reference signal voltage.

The dual integrator ratio circuit 268 includes a comparator circuit 270, a dual inverter stage 280, a flip-flop stage 290, an inverter amplifier 296, a buffer gate amplifier 300, and a pair of operational amplifiers 276, 278 arranged for dual integration. The comparator circuit 270 includes a pair of operational comparators 272, 274, which here take the form of operational amplifiers. The operational amplifier 272 has its positive input terminal connected to the D.C. reference voltage terminal 266 through a resistor 267. The operational amplifier 272 provides a reference comparison output pulse, and the operational amplifier 274 provides a signal comparison output pulse as will be described subsequently.

The dual inverter stage 280 includes a pair of logic amplifiers 282, 284 of the NAND type, and each logic amplifier has at least two input terminals and an output terminal. One of the input terminals of logic amplifier 282 is connected to the output terminal of operational amplifier 272 by conductor 337, and one of the input terminals of logic amplifier 284 is connected to the output terminal of operational amplifier 274 by conductor 338. The remaining input terminals of logic amplifiers 282, 284 are connected in common by conductors 286 and 288, and their junction is connected by conductor 287 to a positive source of voltage in order to maintain one of the inputs of each of the logic amplifiers at a fixed voltage level. The flip-flop stage 290 includes a second pair of NAND logic amplifiers 292, 294 each having two input terminals and an output terminal. One of the inputs of logic amplifier 292 is connected to the output terminal of logic amplifier 282 by conductor 346, and its other input terminal is cross-coupled to the output of logic amplifier 294 by conductor 344. Similarly, logic amplifier 294 has one of its input terminals connected to the output terminal of logic amplifier 284 by conductor 339, and its other input terminal is cross-coupled to the output terminal of logic amplifier 292 by conductor 340. Logic amplifier 294 provides the set action of the flip-flop stage 290, and logic amplifier 292 provides the reset action as will be described subsequently.

The output terminal of logic amplifier 294 is connected to one of the inputs of the inverter amplifier 296 by conductor 342. The inverter amplifier 296 is of the NAND type and has its remaining input terminals 298 connected in common through a conductor 299 to a positive source of voltage in order to maintain them at a fixed voltage level. The output terminal of inverter amplifier 296 is connected through a resistor 348 to the input of a buffer gate amplifier 300. The buffer gate amplifier 300 includes an NPN transistor 301 with the input connection being made to its base terminal. The base of transistor 301 is also connected to a resistor 350 which is in turn connected to a negative D.C. source of voltage by way ofconductor 351. The emitter of transistor 301 is connected to the secondary reference ground conductor 117 through conductor 352. The collector terminal of transistor 301 is connected to a resistor 354 which is in turn connected to one of the positive DC output voltages from the secondary unit power supply 552 of FIG. 1. The collector of transistor 301 is also connected to the gate terminal of a P-channel FET 302 which has its drainsource terminals connected to operate as a switch to control the operation of the dual integrator ratio circuit 268.

The D.C. flow signal voltage at terminal 238 is conducted through a resistor 304 to the negative input terminal of operational amplifier 276 and through a resistor 322 to the negative input terminal of operational amplifier 278. A dual integrated circuit amplifier is used for operational amplifiers 276, 278 in order to reduce the offset voltage and current of these amplifiers to a minimum. As these amplifiers 276, 278 are matched with respect to offset voltage and current, it is not necessary to consider the difference between amplifiers, but it is necessary to bias their initial offsets to zero. The offset bias is accomplished by connecting the positive input terminal of operational amplifier 276 to the positive input terminal of operational amplifier 278 by a conductor 324. The provision of a pair of oppositely-poled diodes 306, 308 connected in parallel between the positive and negative input terminals of amplifier 276 is also made, and amplifier 276 has its positive input terminal connected through conductor 309 to voltage divider network 310. Voltage divider network 310 includes a resistor 312 connected between conductor 309 and reference ground conductor 117 and an offset potentiometer 314 with its movable contact arm 315 connected to the junction between conductor 309 and resistor 312. A resistor 316 is connected between a positive DC. potential and the potentiometer 314, and a resistor 318 is connected between a negative DC. potential, having the same magnitude as the positive potential, and the potentiometer 314. This is provided so that the movable contact arm 315 can be adjusted over a positive to negative range of potentials in order to bias the offset voltages of operational amplifiers 276, 278. The operational amplifier 276 is provided with a capacitor 320 connectedbetween its output terminal and its negative input terminal which, in conjunction with resistor 304, provides an output signal that is an integral function of its input signal.

Operational amplifier 278 has a resistor 326 connected between its output terminal and its negative input terminal which, in conjunction with resistor 322, provides a gain of two. With this gain, the DC. flow signal voltage at the output terminal of operational amplifier 278 is twice that of its input voltage. A resistor 328 is connected between the output terminal of amplifier 278 and the drain terminal of PET 302, and the source terminal of FET 302 is connected to the negative input terminal of operational amplifier 276 through conductor 329. When the drain-source resistance of FET 302 is switched to its low state, the output signal of operational amplifier 278 is supplied to the negative input terminal of operational amplifier 276. When the drain-source resistance of FET 302 is otherwise in its high resistance state, the amplified fiow signal voltage from operational amplifier 278 is not applied to the negative input terminal of operational amplifier 276. The output terminal of operational amplifier 276 is connected through conductor 277 and a resistor 330 into the positive input terminal of operational amplifier 274. The positive input terminal of operational amplifier 274 is also connected by a conductor 334 to the negative input terminal of operational amplifier 272, as well as being connected to the cathode of a Zener diode 331. The Zener diode 331 has its anode connected to conductor 352 which is connected to reference ground conductor 117. The negative input terminal of operational amplifier 274 is connected through a resistor 332 to conductor 352. A capacitor 336 is connected in feedback between the output terminal of operational amplifier 274 and its positive input terminal, and this capacitor 336 is used to provide hysteresis in order to enhance the switching speed of operational amplifier 274 between its off and on states. A similar capacitor 335 is connected between the output terminal and positive input terminal of operational amplifier 272 in order to provide this same effect in its switching operation.

The voltage divider and regulator network 310 also includes a resistor 358 connected between the positive DC. voltage from the secondary unit power supply 552 and resistor 316. The junction of resistor 358 and resistor 316 is connected to the cathode of a Zener diode 360 which has its anode connected to the reference ground conductor 117.' A resistor 362 is connected between the negative voltage from the secondary unit power supply 552 and resistor 318. The anode of a Zener diode 364 is connected to the junction between resistors 362 and 318 and has its cathode connected to the reference ground conductor 117. The Zener diodes 360, 364 are identical in order to provide temperature compensation to the circuit including resistor 316, offset potentiometer314 and resistor 318 so as to provide relatively drift-free operation of the offset balance. A resistor 368 is connected between the positive voltage supplied from secondary unit power supply 552 and conductor 287; Conductor 287 is connected to the cathode of a Zener diode 370 which has its anode connected to the reference ground conductor 117. This last-mentioned circuit connection provides a regulated D.C. voltage for all of the logic amplifiers in the voltage to frequency converter 240 requiring same.

Still referring to FIG. 4, the frequency doubling circuit 376 includes a flip-flop stage 378 having its outputs connected through a summing amplifier 380 into a logic amplifier 382 and through an inverter logic amplifier 384 to the pulse output terminal 428. The flip-flop stage 378 includes a logic amplifier 386 having one of its input terminals connected through conductor 372 to the output terminal of logic amplifier 282. The other input terminal of logic amplifier 386 is connected to the output terminal of logic amplifier 388 through conductor 390. The logic amplifier 388 has one of its input terminals connected to the output terminal of logic amplifier 284 by conductor 374 and has its other input terminal connected to the output terminal of logic amplifier 386 by conductor 392. Both logic amplifiers 386, 388 are of the NAND type. The provision of the flipfiop stage 378 eliminates any noise on the output signal from the dual inverter stage 280 and provides a pair of time related output pulses from the output terminals of logic amplifiers 386, 388. Upon further processing of these output pulses through the frequency doubling circuit 376, a pulse output at terminal 428 is obtained which has a frequency twice that of the frequency of the output wave form of operational amplifier 276 during one full period of integration.

The summing amplifier 380 includes an NPN transistor 398 having its base connected to the output terminal of logic amplifier 386 through a capacitor 396 and also having its base terminal connected through resistor 400 and through conductor 401 to the ground reference conductor 117. The combination of capacitor 396 and resistor 400 provides a differentiating action on the voltage output from logic amplifier 386 in order to provide a spike of voltage to the base terminal of transistor 398. This spike renders transistor 398 conductive for a short instant of time relative to the minimum period of pulses at terminal 428. Transistor 398 has its emitter terminal connected by conductor 402 to conductor 401 and has its collector terminal connected through a resistor 404 and through a conductor 407 to a source of DC. operating voltage. The collector terminal of transistor 398 is also connected by conductor 406 to one of the input terminals of logic amplifier 382. A similar NPN transistor 420 has its base terminal coupled to the output terminal of logic amplifier 388 through a capacitor 418, and a resistor 422 is connected to the base terminal and conductor 401 in order to provide a similar differentiating action on the voltage output of logic amplifier 388. The emitter of transistor 420 is grounded by conductor 424, and the collector is connected to a resistor 426 which is in turn connected to conductor 407. The collector of transistor 420 forms-a second input to logic amplifier 382 by way of conductor 427. The remaining input terminals of logic amplifier 382, designated at 412, are connected to a fixed terminal 410 of a pulse inhibit switch 414. The fixed terminal 410 is connected through a conductor 408 to a fixed level of DC. voltage on which it is dependent for its operation as a NAND type logic amplifier. The output terminal of logic amplifier 382 is connected by conductor 413 to one of the input terminals of the inverter logic amplifier 384, and the other input terminal of logic amplifier 384 is connected to the movable switch arm 416 of the pulse inhibit switch 414. The movable contact arm 416 electrically contacts the fixed contact 410 during normal operation, and it is switched to its electrically open position in order to eliminate the pulse output at terminal 428. This terminal is directly connected to the output terminal of inverter logic amplifier 384.

OPERATION OF THE VOLTAGE TO FREQUENCY CONVERTER The operation of the voltage to frequency converter 240 will be described with reference to the wave forms in FIG. 7(A)(G) showing several wave forms representative of various points in the circuit of FIG. 4. The wave forms shown in FIG. 7 are intended to show the relative time relationships between the triangular wave forms of FIG. 7(A) with respect to the pulses in FIG. 7.(B)-(G).

The first triangular wave form, designated (1) in FIG. 7(A), occupies the time period T along the time axis. This wave form, along with the subsequent triangular wave forms, designated (2), (3), are present at the output terminal 277 of the operational amplifier 276. This corresponds to a particular value of DC. flow signal voltage input on terminal 238 and DC. reference signal voltage input on terminal 266. The triangular wave form in FIG. 7(A), designated (2) and occupying the time period T is representative of a greater flow signal voltage input at terminal 238 relative to the value of flow signal voltage input for the triangular wave form designated (1). Both the triangular wave forms (1) and (2) represent the situation where the reference signal voltage at terminal 266 is the same value, E and the effect of the change in amplitude of the flow signal voltage from a lower value in (1) to a higher value in (2) is reflected by the change from a greater time period T, to a smaller time period T respectively. The triangular wave form designated (3), occupying the time period T is illustrative of the situation where both the flow signal voltage and the reference signal voltage have decreased in value by a certain amount, but the ratio of the reference signal voltage to the flow signal voltage has remained constant. This is indicative that the rate of flow has not changed over time periods T and T Notwithstanding the change in the reference voltage from E for triangular wave form (2) to E for triangular wave form (3), the period T is equal in value to the period T In a similar fashion, if the reference signal voltage increased to a greater negative value and the rate of fluid flow remained unchanged, the flow signal voltage would increase to a higher positive value. The ratio of the reference signal voltage to the flow signal voltage would remain unchanged resulting in a triangular wave form of the same time period of either T or T In this way, the period of the triangular wave forms at the output of operational amplifier 276 are directly proportional to the ratio of reference signal voltage with respect to flow signal voltage while being insensitive to variations occurring during a constant rate of fluid flow.

The operation of amplifier 276 in conjunction with capacitor 320 and input resistor 304 may be defined as set forth in equation (3 1 t dt RY? Where:

e the output voltage of operational amplifier 276 R the value of resistor 304 in ohms C the value of capacitor 320 in farads, and

e, E,, the D.C. flow signal voltage at terminal Now, referring specifically to the triangular wave form (1) occurring in the time period T in FIG. 7(A), equation (3) has two forms, the first of which defines the first half of the wave form occurring in the time interval from zero to t and the second form for the time interval t to t Equation (4) defines the output signal e over the first time interval, and equation (5) is for the second time interval.

E is the D.C. reference signal voltage at terminal 266 Performing the integration on the integrand in equation (4) results in equation (6) which defines e, for the first time interim, from zero to t,.

Because of the action of the logic circuitry within the dual integrator ratio circuit 268, as will be described subsequently, the maximum negative value of the negatively sloping portion of the triangular wave form (1) will be -E,, the D.C. reference voltage signal. At time t t, in equation (6), e -E Substituting the above and solving for t, results in equation (7 Equation (7) also represents an expression for one half the time period "l of the triangular wave form 1) since the time interval from time equal zero to time equals t, is one half of the time period of the triangular wave form, assuming that the flow signal voltage and reference signal voltage have not changed over this period of operation.

Performing the integration on the integrand of equation (5), equation (8) is obtained, and this equation is further modified by substituting the value for time t, at the lower limit of integration as defined by equation (7) to give equation (9).

Equation (9) defines that portion of the triangular wave form (1) between the time interval from t, to t corresponding to the second half period of time period T At time t t e, =0 and solving for t in equation (9) gives equation 10).

t ZE RC/E Equation (10) also provides an expression for the full time period T, since time is cumulative along the abscissa, and t, is a measure of time from time equals zero to time is equal to t The frequency in cycles per second of triangular wave form (1) is the reciprocal of T, as presented in equation (1 l fl l IsI 2 (In it should be understood that the above analytical relationships are also true for the triangular wave forms (2), (3) with the exception that in the triangular wave form (2), the value of E is greater, corresponding to a greater fluid flow rate. The value for the reference signal voltage is diminished for triangular wave form (3), so E is substituted for E in all of the above relationships. It should also be recognized that the ratio of reference signal voltage with respect to flow signal voltage is the same for triangular wave form (2) as it is for triangular wave form (3). As was previously explained, the time periods T T are equal even though the shape of triangular wave form (2) is different from the shape of triangular wave form (3) corresponding to a constant rate of fluid flow over these time intervals during a variation in supply voltage to the flowmeter system.

The operation of the dual integrator ratio circuit 268 is further described with reference to FIG. 7(B)-(F) which show wave forms representative of various points in the logic circuitry. FIG. 7 (B) shows the output pulses on conductor 338 which are at the output terminal of operational amplifier 274. An output pulse of relatively brief duration occurs on conductor 338 each time that the triangular wave form from the output terminal of operational amplifier 276 reaches zero volts. This condition is reached at the termination of the positively sloping leg at the close of the second half period of each triangular wave form. The biasing arrangement, including resistor 332 connected through conductor 352 to the reference ground conductor 117, dictates that the output of operational amplifier 274 is substantially zero when the signal input to its positive input terminal is negative. A positive output pulse is provided at 

1. A measuring system for comparing the relative magnitudes of a first and a second D.C. input signal, said system comprising: means for symmetrically integrating said first signal between time period intervals proportional to its magnitude relative to the magnitude of said second signal; switching means for periodically reinitiating said symmetrical integrating cycle; and pulse generating means responsive to the half-period cycles of said symmetrical integrating means so that output pulses are generated at a frequency which is a multiple of said integrating cycle.
 2. The measuring system of claim 1 wherein said symmetrical integrating means includes a pair of substantially matched operational amplifiers each having a pair of oppositely poled input terminals and an output terminal, said amplifiers having one set of like poled input terminals connected in common and the other set of like poled input terminals coupled to said first input signal, said first amplifier having twice the gain of said second amplifier and said second amplifier including a feedback capacitor for integral action connected between its output terminal and its said input terminal coupled to said first input signal, said first amplifier having its output terminal coupled to the feedback input terminal of said second amplifier through said switching means so that the output signal at the output terminal of said second amplifier has a substantially triangular wave form with a half-wave periodicity directly proportional to the ratio of said second input signal and said first input signal.
 3. The measuring system of claim 2 wherein said switching means includes means for comparing the output signal from said second amplifier with both said second input signal and with a ground reference potential, said comparing means providing a first pulSe output whenever the output signal from said second amplifier is substantially equal to said second input signal and providing a second pulse output whenever the output signal from said second amplifier is substantially equal to said ground reference potential.
 4. The measuring system of claim 3 wherein said switching means further includes flip-flop means for controlling the application of the output signal of said first amplifier to the feedback input terminal of said second amplifier, said flip-flop means being responsive to said first pulse output of said comparing means to apply the output signal of said first amplifier until said flip-flop means is reset in response to said second pulse output of said comparing means.
 5. The measuring system of claim 3 wherein said pulse generating means responsive to the half-period cycles of said symmetrical integrating means includes flip-flop means for responding to said first and second output pulses of said comparing means, differentiating circuit means coupled to the outputs of said flip-flop means for providing a gating spike in time synchronism with each of said output pulses of said comparing means, and summing means responsive to the gating spikes for providing output pulses at twice the frequency of said integrating cycle.
 6. In a measuring system, a frequency to voltage converter comprising: means for producing a frequency variable train of pulses, each of the pulse cycles of said train of pulses having the corresponding periodicity of the variable input frequency and each said pulse having a substantially constant pulse width; means for voltage converting said pulse cycles of said train to form a substantially square wave signal varying plus and minus of a reference level, said deviations of one polarity having a substantially constant width synchronized with said constant width pulses and said deviations of said other polarity being synchronized with the remainder of each pulse cycle; a voltage source having an output signal; series-shunt chopper means, coupled to said square wave signal, for modulating said voltage source output signal during said plus deviations; flip-flop means for gating said voltage converting means and single shot multi-vibrator means, responsive to said flip-flop means, for resetting said flip-flop means to produce said pulses having a substantially constant pulse width; and means for averaging the modulated output signal of the voltage source to provide an averaged output voltage which is proportional to the product of the modulated output signal of the voltage source and the input frequency.
 7. The measuring system of claim 6 wherein said voltage source having an output signal includes second output signal means for producing an adjustable D.C. voltage which when added to the averaged output voltage of said averaging means provides an adjustable D.C. bias. 